The present invention relates to a multiplexer/demultiplexer for high speed switching applications.
The multiplier stage of conventional multiplexer/demultiplexer circuitry usually comprises a sync pattern generator, an address counter and an array of gates. The address counter is reset at frame intervals by a sync from the frame pattern generator to successively increment its count at slot intervals to generate a binary count. The output of the counter is used as an address for accessing each of the multiplexer gates for multiplexing data bits into specified time slots of a data bit stream. The demultiplexer stage of the circuitry includes an array of gates, a frame synchronizer and a second counter. The frame synchronizer detects the sync pattern of the data bit stream to cause the second counter to synchronize with the slot timing of the bit stream to increment its binary count. The demultiplexer gates are respectively enabled by the address counts of the second counter to demultiplex the individual data bits into output terminals.
LSI chips currently available for high speed switching operations have a level of integration which is lower than is required for implementing multiplexers and demultiplexers of the above mentioned type due to their complexity.